#if defined(TSINGMA_MX) || defined(TSINGMA_GX)

#include "usw/include/drv_common.h"
#include "usw/include/drv_sdb.h"
#include "usw/include/drv_app.h"
#include "usw/include/drv_io.h"

extern int32
drv_ser_get_tcam_memory_info_from_error_addr(uint8 lchip, uint32 error_addr, uint32* mem_id, uint32* entry_index, uint32* tcam_mem_id);
extern int32
drv_usw_chip_read_sram_entry(uint8 lchip, uint64 addr, uint32* data, int32 len);
extern int32
drv_usw_chip_reg_read(uint8 lchip, uint32 tbl_id, uint32 index, uint8 oper_bmp, uint32* data);
extern int32
drv_usw_chip_reg_write(uint8 lchip, uint32 tbl_id, uint32 index, uint8 oper_bmp, uint32* data);

int32
drv_tmm_ser_get_mem_desc_index(uint8 lchip, uint32 mem_id, uint32* p_desc_index)
{
#if (SDK_WORK_PLATFORM == 0)
    if (DRV_FTM_TCAM_KEY0 <= mem_id && mem_id < DRV_FTM_TCAM_KEY26)
    {
        *p_desc_index = mem_id - DRV_FTM_TCAM_KEY0;
    }
    else if (DRV_FTM_LPM_TCAM_KEY0 <= mem_id && mem_id < DRV_FTM_LPM_TCAM_KEY6)
    {
        *p_desc_index = (mem_id - DRV_FTM_LPM_TCAM_KEY0) + DRV_CONST(DRV_MAX_NOR_TCAM_NUM);
    }
    else if (DRV_FTM_CID_TCAM == mem_id || DRV_FTM_SEL_TCAM == mem_id)
    {
        *p_desc_index =  (mem_id - DRV_FTM_CID_TCAM) + DRV_CONST(DRV_MAX_LPM_TCAM_NUM) + DRV_CONST(DRV_MAX_NOR_TCAM_NUM);
    }
    else if(DRV_FTM_UDF_TCAM == mem_id || DRV_FTM_RMAC_TCAM == mem_id )
    {
        *p_desc_index =  (mem_id - DRV_FTM_CID_TCAM - 1) + DRV_CONST(DRV_MAX_LPM_TCAM_NUM) + DRV_CONST(DRV_MAX_NOR_TCAM_NUM);
    }
    else
    {
        return DRV_E_INVALID_PARAMETER;
    }
#endif
    return DRV_E_NONE;
}

int32
drv_tmm_ser_dma_recover_tcam(uint8 lchip, void* p_param)
{
    uint32 cmd = 0, cmd1 = 0;
    uint32 error_addr = 0;
    uint32 entry_index = 0;
    uint32 tcam_mem_id = 0, tbl_id = 0;
    drv_ser_master_t    *p_drv_ser_master = p_drv_master[lchip]->p_ser_master;
    drv_sdb_t           *p_sdb = g_sdb_master[lchip];
    drv_ser_cb_info_t ser_cb_info;
    DmaTcamScanPtr_m scan_ptr;
    DmaTcamScanLog_m scan_log;
    uint32 scan_valid = 0;
    uint32 process_cnt = 0;
    uint32 p_data_buffer[16] = {0};

    cmd  = DRV_IOR(DmaTcamScanPtr_t, DRV_ENTRY_FLAG);
    DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &scan_ptr));
    GetDmaTcamScanPtr(A, tcamScanLogValid_f, &scan_ptr, &scan_valid);
    cmd1 = DRV_IOR(DmaTcamScanLog_t, DRV_ENTRY_FLAG);

    while(scan_valid != 0)
    {
        /*read hw addr*/
        DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd1, &scan_log));
        GetDmaTcamScanLog(A, tcamScanAddr_f, &scan_log, &error_addr);
        DRV_DBG_INFO("Error Memory Address:0x%X\n", error_addr);
        if (!error_addr)
        {
            break;
        }

        /*get mem_id and offset*/
        DRV_IF_ERROR_RETURN(drv_ser_get_tcam_memory_info_from_error_addr(lchip, error_addr, &tcam_mem_id, &entry_index, &tbl_id));
        /*restore hw*/
        drv_usw_chip_write_sram_entry(lchip, error_addr|0x1, (uint32*)(p_sdb->static_tbl[tbl_id]+entry_index*TABLE_ENTRY_OFFSET(lchip, tbl_id)), TABLE_ENTRY_SIZE(lchip, tbl_id));
        DRV_DBG_INFO("Error Memory tbl_id:%s entry_index %d\n", TABLE_NAME(lchip, tbl_id), entry_index);
        drv_usw_chip_read_sram_entry(lchip, error_addr|0x1, p_data_buffer, TABLE_ENTRY_SIZE(lchip, tbl_id));
        DRV_SDB_TCAM_XY2DM(p_data_buffer, ((TABLE_ENTRY_SIZE(lchip, tbl_id) >> 3) << 2));

        /*report error*/
        ser_cb_info.type = DRV_SER_TYPE_TCAM_ERROR;
        ser_cb_info.tbl_id = 0xFE000000 + tcam_mem_id;
        ser_cb_info.tbl_index = TABLE_ENTRY_SIZE(lchip, tbl_id) * entry_index;
        ser_cb_info.tbl_id |= TABLE_ENTRY_SIZE(lchip, tbl_id) << 18;
        ser_cb_info.recover = (sal_memcmp((uint8*)p_data_buffer, (uint8*)(p_sdb->static_tbl[tbl_id]+entry_index*TABLE_ENTRY_OFFSET(lchip, tbl_id)), TABLE_ENTRY_SIZE(lchip, tbl_id))? 2 :1);
        ser_cb_info.action = DRV_SER_ACTION_LOG;
        ser_cb_info.intr_type = NULL;
        drv_ser_report_ser_event_cb(lchip, &ser_cb_info);
        (p_drv_ser_master->recover_tcam_key)++;

        /*do loop*/
        DRV_IF_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &scan_ptr));
        GetDmaTcamScanPtr(A, tcamScanLogValid_f, &scan_ptr, &scan_valid);
        process_cnt ++;
        if (process_cnt == 1024)
        {
            break;
        }
    }

    return DRV_E_NONE;
}

STATIC INLINE int32
_drv_tmm_acc_get_hash_type_by_tbl_id(uint8 lchip, uint32 tbl_id, uint32* p_hash_type, uint32* p_hash)
{
   uint32 out = 0;

   switch(tbl_id)
   {
   case DsFibHost0FcoeHashKey_t:
       out  =  DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_FCOE);
       break;

   case DsFibHost0Ipv4HashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV4);
       SetDsFibHost0Ipv4HashKey(V, pointer_f, p_hash, 0);
       break;

    case DsFibHost0MacIpv4McastHashKey_t:
        out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV4MCAST);
        SetDsFibHost0Ipv4HashKey(V, pointer_f, p_hash, 0);
        break;

   case DsFibHost0Ipv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6MCAST);
       SetDsFibHost0Ipv6McastHashKey(V, pointer_f, p_hash, 0);
       break;

   case DsFibHost0Ipv6UcastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_IPV6UCAST);
       break;

   case DsFibHost0MacIpv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_MACIPV6MCAST);
       SetDsFibHost0MacIpv6McastHashKey(V, pointer_f, p_hash, 0);
       break;

   case DsFibHost0TrillHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST0PRIMARYHASHTYPE_TRILL);
       break;

    case DsFlowL2HashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_L2);
       break;

    case DsFlowL2L3HashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_L2L3);
       break;

    case DsFlowL3Ipv4HashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_L3IPV4);
       break;

    case DsFlowL3Ipv6HashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_L3IPV6);
       break;

    case DsFlowL3MplsHashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_L3MPLS);
       break;

    case DsFlowNshForwardHashKey_t:
       out  = DRV_CONST(DRV_FLOWHASHTYPE_NSH);
       break;

    case DsFibHost1FcoeRpfHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_FCOERPF);
       break;

    case DsFibHost1Ipv4McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4MCAST);
       break;

    case DsFibHost1Ipv4NatDaPortHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATDAPORT);
       break;

    case DsFibHost1Ipv4NatSaPortHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV4NATSAPORT);
       break;

    case DsFibHost1Ipv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6MCAST);
       break;

    case DsFibHost1Ipv6NatDaPortHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATDAPORT);
       break;

    case DsFibHost1Ipv6NatSaPortHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_IPV6NATSAPORT);
       break;

    case DsFibHost1MacIpv4McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV4MCAST);
       break;

    case DsFibHost1MacIpv6McastHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_MACIPV6MCAST);
       break;


    case DsFibHost1TrillMcastVlanHashKey_t:
       out  = DRV_CONST(DRV_FIBHOST1HASHTYPE_TRILLMCASTVLAN);
       break;


   default:
       return DRV_E_INVAILD_TYPE;
   }

    *p_hash_type = out;

    return 0;
}

STATIC int32
_drv_tmm_acc_prepare_fib_hash_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    FibHashCpuLookupReq_m host1_req;
    FibHashCpuLookupResult_m host1_result;
    int32 ret = 0;
    uint8 length = 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint8 req_interface = 0;
    uint32 hash_type = 0;
    DsFibHost1Ipv4McastHashKey_m* p_hash = NULL;
    ds_fib_cpu_look_req_tmm_t* p_host1_req;
    ds_fib_cpu_look_res_tmm_t* p_host1_res;
 #if(SDK_WORK_PLATFORM == 0)
    uint32     req_val = 0;
 #endif

    sal_memset(&host1_req, 0, sizeof(host1_req));
    /*for action by key, need do lookup first*/
    pre_info->tbl_id = in->tbl_id;
    p_host1_req = (ds_fib_cpu_look_req_tmm_t*)&host1_req;
    p_host1_res = (ds_fib_cpu_look_res_tmm_t*)&host1_result;

    length  = TABLE_ENTRY_SIZE(lchip, in->tbl_id);
    sal_memcpy((uint8*)p_host1_req, (uint8 *)in->data, length);
    p_hash = (DsFibHost1Ipv4McastHashKey_m*)p_host1_req;
    mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
          ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    if (pre_info->hash_type == DRV_ACC_HASH_MODULE_FIB_HOST0)
    {
        req_interface = 2;
        _drv_tmm_acc_get_hash_type_by_tbl_id(lchip, in->tbl_id, &hash_type, (uint32*)p_hash);
        p_host1_req->hash_key_type = hash_type;
        if (length == DRV_CONST(DRV_HOST0_SINGLE_KEY_BYTE))
        {
            SetDsFibHost0Ipv4HashKey(V, valid_f, p_hash, 1);
        }
        else if(length == DRV_CONST(DRV_HOST0_DOUBLE_KEY_BYTE))
        {
            SetDsFibHost0Ipv6UcastHashKey(V, valid0_f, p_hash, 1);
            SetDsFibHost0Ipv6UcastHashKey(V, valid1_f, p_hash, 1);
        }
        /*Clear adindex*/
        SetDsFibHost0Ipv4HashKey(V, dsAdIndex_f, p_hash, 0);
    }
    else if(pre_info->hash_type == DRV_ACC_HASH_MODULE_FLOW)
    {
        req_interface = 1;
        SetDsFlowL2HashKey(V, dsAdIndex_f, p_hash, 0);
        hash_type = GetDsFlowL2HashKey(V, hashKeyType_f, p_hash);
        p_host1_req->hash_key_type = hash_type;
    }
    else /*fib host 1*/
    {
        req_interface = 0;
        /*Clear adindex*/
        SetDsFibHost1Ipv4McastHashKey(V, dsAdIndex_f, p_hash, 0);
        
         /*only for TMM*/
        _drv_tmm_acc_get_hash_type_by_tbl_id(lchip, in->tbl_id, &hash_type, (uint32*)p_hash);
        p_host1_req->hash_key_type = hash_type;
    }

    p_host1_req->req_valid = 1;
    p_host1_req->length_mode = mode;
    p_host1_req->req_interface = req_interface;

    DRV_APP_REG_IOW(lchip,FibHashCpuLookupReq_t,(uint32*)p_host1_req, in->oper_bmp);
#if(SDK_WORK_PLATFORM == 0)
    DRV_ENTRY_LOCK(lchip);
#endif

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
#if(SDK_WORK_PLATFORM == 0)
         if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
         {
            not_done = 0;
            break;
         }
         p_drv_master[lchip]->drv_chip_read(DRV_MAP_LDEV(lchip),  DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_FIB)),1, &req_val);
          not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_FIB)));
#else
        DRV_APP_REG_IOR(lchip, FibHashCpuLookupReq_t, p_host1_req, DRV_ACC_PP_EN);
        not_done = p_host1_req->req_valid;
#endif
       if (!not_done)
        {
            break;
        }
       DRV_ACC_WAIT_SLEEP;
    }
#if(SDK_WORK_PLATFORM == 0)
        DRV_ENTRY_UNLOCK(lchip);
#endif
    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
     DRV_APP_REG_IOR(lchip, FibHashCpuLookupResult_t, (uint32*)p_host1_res, DRV_ACC_PP_EN);

    pre_info->conflict = p_host1_res->conflict;
    pre_info->valid = p_host1_res->lookup_result_valid;
    /*acording lookup result build prepare information*/
    if (!p_host1_res->conflict)
    {
        pre_info->key_index = p_host1_res->result_idx;
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;
    return ret;
}

STATIC int32
_drv_tmm_acc_prepare_egress_scl_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    EgressSclCpuLookupReq_m egress_scl_req;
    EgressSclCpuLookupResult_m egress_scl_result;
    int32  ret = 0;
    uint32 loop = 0;
    uint32 not_done = 1;
    uint8 length = SINGLE_KEY_BYTE;
    ds_escl_cpu_look_req_tmm_t* p_escl_req;
    ds_escl_cpu_look_res_tmm_t* p_escl_res;
#if(SDK_WORK_PLATFORM == 0)
    uint32 req_val = 0;
#endif

    sal_memset(&egress_scl_req, 0, sizeof(EgressSclCpuLookupReq_m));
    p_escl_req = (ds_escl_cpu_look_req_tmm_t*)&egress_scl_req;
    p_escl_res = (ds_escl_cpu_look_res_tmm_t*)&egress_scl_result;
    /*for action by key, need do lookup first*/
    sal_memcpy((uint8*)p_escl_req, (uint8 *)in->data, length);
    /*mask ad info*/
    sal_memset(&(((uint32*)p_escl_req)[3]), 0, DRV_BYTES_PER_WORD);
    p_escl_req->req_valid = 1;
    DRV_APP_REG_IOW(lchip, EgressSclCpuLookupReq_t, p_escl_req, DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#if(SDK_WORK_PLATFORM == 0)
        DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_EGRESSSCL)), &req_val));
        not_done = (req_val & 1); /* DRV_ACCREQ_BITOFFSET_EGRESSSCL is 0 */
#else
        DRV_APP_REG_IOR(lchip, EgressSclCpuLookupReq_t, p_escl_req, DRV_ACC_PP_EN);
        not_done = p_escl_req->req_valid;
#endif

        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,EgressSclCpuLookupResult_t, p_escl_res, DRV_ACC_PP_EN);
    if (in->level)
    {
        pre_info->conflict = p_escl_res->conflict1;
        pre_info->valid = p_escl_res->result_valid1;

        /*acording lookup result build prepare information*/
        if (!p_escl_res->conflict1)
        {
            pre_info->key_index = p_escl_res->result_idx1;
        }
        pre_info->tcam_hit = p_escl_res->is_tcam_hit1;
    }
    else
    {
        pre_info->conflict = p_escl_res->conflict0;
        pre_info->valid = p_escl_res->result_valid0;

        /*acording lookup result build prepare information*/
        if (!p_escl_res->conflict0)
        {
            pre_info->key_index = p_escl_res->result_idx0;
        }
        pre_info->tcam_hit = p_escl_res->is_tcam_hit0;
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;

    return ret;
}

STATIC int32
_drv_tmm_acc_prepare_userid_by_key(uint8 lchip, drv_acc_in_t* in, drv_cpu_acc_prepare_info_t* pre_info)
{
    UserIdCpuLookupReq_m userid_req;
    UserIdCpuLookupResult_m userid_result;
    ds_scl_cpu_look_req_tmm_t* p_scl_req;
    ds_scl_cpu_look_res_tmm_t* p_scl_result;
    int32  ret = 0;
    uint8  length= 0;
    uint32 mode = 0;
    uint32 loop = 0;
    uint32 not_done = 1;    
    DsUserIdCvlanPortHashKey_m* p_hash = NULL;
#if(SDK_WORK_PLATFORM == 0)
    uint32   req_val = 0;
#endif
    sal_memset(&userid_req, 0, sizeof(UserIdCpuLookupReq_m));
    p_scl_req = (ds_scl_cpu_look_req_tmm_t*)&userid_req;
    p_scl_result = (ds_scl_cpu_look_res_tmm_t*)&userid_result;
    /*for action by key, need do lookup first*/
    length  = TABLE_ENTRY_SIZE(lchip, in->tbl_id);
    mode = (length == SINGLE_KEY_BYTE) ? HASH_KEY_LENGTH_MODE_SINGLE:
           ((length == DOUBLE_KEY_BYTE)?HASH_KEY_LENGTH_MODE_DOUBLE:HASH_KEY_LENGTH_MODE_QUAD);

    sal_memcpy((uint8*)p_scl_req, (uint8 *)in->data, length);
    p_hash = (DsUserIdCvlanPortHashKey_m*)p_scl_req;
    SetDsUserIdCvlanPortHashKey(V, dsAdIndex_f, p_hash, 0);

    if (in->level == 1)
    {
        p_scl_req->req_interface = 1;
    }

    p_scl_req->req_valid = 1;
    p_scl_req->length_mode = mode;
    DRV_APP_REG_IOW(lchip,UserIdCpuLookupReq_t, p_scl_req, DRV_ACC_PP_EN);

    for (loop = 0; (loop < DRV_APP_LOOP_CNT) && not_done; loop++)
    {
        if (p_drv_master[lchip]->wb_status == DRV_WB_STATUS_RELOADING)
        {
            not_done = 0;
            break;
        }
#if(SDK_WORK_PLATFORM == 0)
          DRV_IF_ERROR_RETURN(drv_usw_chip_read(lchip, DRV_ADDR_PP_EN(DRV_CONST(DRV_ACCREQ_ADDR_USERID)), &req_val));
          not_done = (req_val & (1 << DRV_CONST(DRV_ACCREQ_BITOFFSET_USERID)));
#else
          DRV_APP_REG_IOR(lchip, UserIdCpuLookupReq_t, p_scl_req, DRV_ACC_PP_EN);
          not_done = p_scl_req->req_valid;
#endif
        if (!not_done)
        {
            break;
        }
        DRV_ACC_WAIT_SLEEP;
    }

    if (not_done)
    {
         return DRV_E_CMD_NOT_DONE;
    }
    DRV_APP_REG_IOR(lchip,UserIdCpuLookupResult_t, p_scl_result, DRV_ACC_PP_EN);

    pre_info->conflict = p_scl_result->conflict;
    pre_info->valid = p_scl_result->result_valid;

    /*acording lookup result build prepare information*/
    if (!p_scl_result->conflict)
    {
        pre_info->key_index = p_scl_result->result_idx;
    }
    pre_info->is_cam = pre_info->key_index < pre_info->cam_num;

    return ret;
}

STATIC int32
_drv_tmm_acc_prepare_write_mac_by_idx(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    hw_mac_addr_t   mac = {0};
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;
    uint32 req_type = DRV_ACC_CHIP_MAC_WRITE_BY_INDEX;

    
    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;
    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;

    mac[0] = (p_mac_key->mappedMac_0_25|((p_mac_key->mappedMac_26_47&0x3f)<<26));
    mac[1] = ((p_mac_key->mappedMac_26_47>>6)&0xffff);

    fib_req->req_valid = 1;
    fib_req->req_type = req_type;
    fib_req->key_mac_23_47 = (((mac[1]&0xffff)<<9)|((mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (mac[0]&0x7fffff);
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));
    fib_req->key_ad_index_7_17 = ((p_mac_key->dsAdIndex>>7)&0x7ff);
    fib_req->key_ad_index_0_6 = (p_mac_key->dsAdIndex&0x7f);
    fib_req->key_index_6_21 = ((in->index>>6)&0xffff);
    fib_req->key_index_0_5 = (in->index&0x3f);

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_write_mac_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index       = 0;
    uint32 static_count_en = 0;
    uint32 hw_aging_en = 0;
    hw_mac_addr_t   mac = {0};
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;
    uint32 req_type = DRV_ACC_CHIP_MAC_WRITE_BY_KEY;
    DRV_PTR_VALID_CHECK(in->data);

    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;
    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;

    mac[0] = (p_mac_key->mappedMac_0_25|((p_mac_key->mappedMac_26_47&0x3f)<<26));
    mac[1] = ((p_mac_key->mappedMac_26_47>>6)&0xffff);

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 14;    /* port mac limit */
        key_index |= 1 << 15;    /* vlan mac limit */

        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
        {
            key_index |= 1 << 16;    /* dynamic mac limit */
        }
    }

    if (DRV_IS_BIT_SET(in->flag, DRC_ACC_PROFILE_MAC_LIMIT_EN))
    {
        key_index |= 1 << 17;    /* profile mac limit */
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
    {
        /*logic port do not update port mac limit*/
        key_index &= ~(1<<14);
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
    {
        static_count_en = 1;
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_AGING_EN))
    {
        hw_aging_en = 1;
    }

    fib_req->req_valid = 1;
    fib_req->req_type = req_type;
    fib_req->key_mac_23_47 = (((mac[1]&0xffff)<<9)|((mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (mac[0]&0x7fffff);
    fib_req->static_count_en = static_count_en;
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));
    fib_req->key_ad_index_7_17 = ((p_mac_key->dsAdIndex>>7)&0x7ff);
    fib_req->key_ad_index_0_6 = (p_mac_key->dsAdIndex&0x7f);
    fib_req->req_port_13_15 = ((in->gport>>13)&0x7);
    fib_req->req_port_0_12 = (in->gport&0x1fff);
    fib_req->key_index_6_21 = ((key_index>>6)&0xffff);
    fib_req->key_index_0_5 = (key_index&0x3f);
    fib_req->key_del_type = in->timer_index;
    fib_req->key_port_del_mode = hw_aging_en;

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_del_mac_by_idx(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;
    fib_req->req_valid = 1;
    fib_req->req_type = DRV_ACC_CHIP_MAC_DEL_BY_INDEX;
    fib_req->key_index_6_21 = ((in->index>>6)&0xffff);
    fib_req->key_index_0_5 = (in->index&0x3f);
    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_del_mac_by_key(uint8 lchip, drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index = 0;
    hw_mac_addr_t   mac = {0};
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;
    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;

    mac[0] = (p_mac_key->mappedMac_0_25|((p_mac_key->mappedMac_26_47&0x3f)<<26));
    mac[1] = ((p_mac_key->mappedMac_26_47>>6)&0xffff);
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 14;    /* port mac limit */
        key_index |= 1 << 15;    /* vlan mac limit */
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
        {
            key_index |= 1 << 16;    /* dynamic mac limit */
        }
    }

    if (DRV_IS_BIT_SET(in->flag, DRC_ACC_PROFILE_MAC_LIMIT_EN))
    {
        key_index |= 1 << 17;    /* profile mac limit */
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
    {
        /*logic port do not update port mac limit*/
        key_index &= ~(1<<14);
    }

    fib_req->req_valid = 1;
    fib_req->req_type = DRV_ACC_CHIP_MAC_DEL_BY_KEY;
    fib_req->key_mac_23_47 = (((mac[1]&0xffff)<<9)|((mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (mac[0]&0x7fffff);
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));
    fib_req->key_index_6_21 = ((key_index>>6)&0xffff);
    fib_req->key_index_0_5 = (key_index&0x3f);

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_lkp_fib0_by_idx(uint8 lchip, drv_acc_in_t* in, uint32* cpu_req)
{
    uint32        length_mode= 0;
    hw_mac_addr_t hw_mac     = { 0 };
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;
    hw_mac[0] = in->index ;

    if ((in->tbl_id == DsFibHost0FcoeHashKey_t) || (in->tbl_id == DsFibHost0Ipv4HashKey_t)
        || (in->tbl_id == DsFibHost0MacHashKey_t) || (in->tbl_id == DsFibHost0TrillHashKey_t))
    {
        length_mode = HASH_KEY_LENGTH_MODE_SINGLE;
    }
    else
    {
        length_mode = HASH_KEY_LENGTH_MODE_DOUBLE;
    }

    fib_req->req_valid = 1;
    fib_req->req_type = DRV_ACC_CHIP_HOST0_lOOKUP_BY_INDEX;
    fib_req->key_mac_23_47 = (((hw_mac[1]&0xffff)<<9)|((hw_mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (hw_mac[0]&0x7fffff);
    fib_req->key_port_del_mode = length_mode;

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_lkp_mac_by_key(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    hw_mac_addr_t   mac = {0};
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;
    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;

    mac[0] = (p_mac_key->mappedMac_0_25|((p_mac_key->mappedMac_26_47&0x3f)<<26));
    mac[1] = ((p_mac_key->mappedMac_26_47>>6)&0xffff);

    fib_req->req_valid = 1;
    fib_req->req_type = DRV_ACC_CHIP_MAC_LOOKUP_BY_KEY;
    fib_req->key_mac_23_47 = (((mac[1]&0xffff)<<9)|((mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (mac[0]&0x7fffff);
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_dump(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32        del_type  = 0;
    uint32        del_mode  = 0;
    uint32        key_index = 0;
    hw_mac_addr_t hw_mac    = { 0 };
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    uint32 req_type = 0;
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    hw_mac[0] = (in->index & 0x1FFFFF) |
                 ((in->query_end_index & 0x7) << 21) |
                 (((in->query_end_index >> 3) & 0xff) << 24);

    hw_mac[1] = (in->query_end_index >> 11) & 0x3FF;
    key_index |= 1<<4;   /*Dump no pending*/
    if(in->op_type == DRV_ACC_OP_BY_ALL)
    {
         req_type = DRV_ACC_CHIP_MAC_FLUSH_DUMP_BY_ALL;
         del_mode = 1;

          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_UCAST))
          {
              key_index |= 1<<2;
          }
         if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_MCAST))
          {
              key_index |= 1 << 3;
          }
          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_PENDING))
          {
              key_index &= ~(1 << 4); /*do not dump no-pending*/
              key_index |= 1 << 5;
          }
    }
    else
    {
          req_type = DRV_ACC_CHIP_MAC_DUMP_BY_PORT_VLAN;
          if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
          {
             del_mode = 1;
              key_index |= (1 << 3);
          }
          if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN))
           {    /*dump by port+vsi*/
               del_type = 0;
           }
           else if (in->op_type == DRV_ACC_OP_BY_PORT)
           {    /*dump by port*/
               del_type = 1;
           }
           else if (in->op_type == DRV_ACC_OP_BY_VLAN)
           {    /*dump by vsi*/
               del_type = 2;
           }
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC))
    {
        key_index |= 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
    {
        key_index |= 1 << 1;
    }

    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;
    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;

    fib_req->req_valid = 1;
    fib_req->req_type = req_type;
    fib_req->key_mac_23_47 = (((hw_mac[1]&0xffff)<<9)|((hw_mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (hw_mac[0]&0x7fffff);
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));
    fib_req->key_ad_index_7_17 = ((in->query_cnt>>7)&0x7ff);
    fib_req->key_ad_index_0_6 = (in->query_cnt&0x7f);
    fib_req->req_port_13_15 = ((in->gport>>13)&0x7);
    fib_req->req_port_0_12 = (in->gport&0x1fff);
    fib_req->key_index_6_21 = ((key_index>>6)&0xffff);
    fib_req->key_index_0_5 = (key_index&0x3f);
    fib_req->key_del_type = del_type;
    fib_req->key_port_del_mode = del_mode;

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_prepare_flush(uint8 lchip,  drv_acc_in_t* in, uint32* cpu_req)
{
    uint32 key_index = 0;
    uint32 del_type  = 0;
    uint32 del_mode  = 0;
    sys_fdbkey_encode_tmm_t* p_mac_key = NULL;
    hw_mac_addr_t   mac = {0};
    uint32 req_type = 0;
    ds_fib_hash_cpu_req_tmm_t* fib_req = NULL;

    if (in->op_type == DRV_ACC_OP_BY_ALL)
    {
       req_type = DRV_ACC_CHIP_MAC_FLUSH_DUMP_BY_ALL;
    }
    else if ((in->op_type == DRV_ACC_OP_BY_PORT) ||
       (in->op_type == DRV_ACC_OP_BY_VLAN) ||
       (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN)))
    {
       req_type = DRV_ACC_CHIP_MAC_FLUSH_BY_PORT_VLAN;

       if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_VLAN))
        {    /*delete by port+vsi*/
            del_type = 0;
        }
        else if (in->op_type == DRV_ACC_OP_BY_PORT)
        {    /*delete by port*/
            del_type = 1;
        }
        else if (in->op_type == DRV_ACC_OP_BY_VLAN)
        {    /*delete by vsi*/
            del_type = 2;
        }
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
         {
             /*logic port do not update port mac limit*/
             key_index &= ~(1<<5);
             del_mode = 1;
             key_index |= (1 << 3);
         }
    }
    else if ((in->op_type == DRV_ACC_OP_BY_MAC)||
       (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_MAC)))
    {
        req_type = DRV_ACC_CHIP_MAC_FLUSH_BY_MAC_PORT;
        if (in->op_type == (DRV_ACC_OP_BY_PORT | DRV_ACC_OP_BY_MAC))
         {    /*delete by mac+port*/
             del_type = 2;
         }
         else
         {    /*delete by mac*/
             del_type = 1;
         }
        if (DRV_IS_BIT_SET(in->flag, DRV_ACC_USE_LOGIC_PORT))
         {
             /*logic port do not update port mac limit*/
             key_index &= ~(1<<5);
             del_mode = 1;
         }
    }

    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_STATIC))
    {
        key_index |= 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_ENTRY_DYNAMIC))
    {
        key_index |= 1 << 1;
    }
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_UPDATE_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 5;
        key_index |= 1 << 7;
        key_index |= 1 << 11;
    }

    /*profile*/
    key_index |= 1 << 9;
    if (DRV_IS_BIT_SET(in->flag, DRV_ACC_STATIC_MAC_LIMIT_CNT))
    {
        key_index |= 1 << 4;
        key_index |= 1 << 6;
        key_index |= 1 << 8;
    }

    fib_req = (ds_fib_hash_cpu_req_tmm_t*)cpu_req;
    p_mac_key = (sys_fdbkey_encode_tmm_t*)in->data;
    mac[0] = (p_mac_key->mappedMac_0_25|((p_mac_key->mappedMac_26_47&0x3f)<<26));
    mac[1] = ((p_mac_key->mappedMac_26_47>>6)&0xffff);

    fib_req->req_valid = 1;
    fib_req->req_type = req_type;
    fib_req->key_mac_23_47 = (((mac[1]&0xffff)<<9)|((mac[0]>>23)&0x1ff));
    fib_req->key_mac_0_22 = (mac[0]&0x7fffff);
    fib_req->key_vrf_id = (p_mac_key->vsiId_0_8 | ((p_mac_key->vsiId_9_14&0x3f)<<9));
    fib_req->req_port_13_15 = ((in->gport>>13)&0x7);
    fib_req->req_port_0_12 = (in->gport&0x1fff);
    fib_req->key_index_6_21 = ((key_index>>6)&0xffff);
    fib_req->key_index_0_5 = (key_index&0x3f);
    fib_req->key_del_type = del_type;
    fib_req->key_port_del_mode = del_mode;

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_result_write_mac_by_key(uint8 lchip,drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    ds_fib_hash_cpu_res_tmm_t* p_cpu_res = NULL;

    p_cpu_res = (ds_fib_hash_cpu_res_tmm_t*)fib_acc_cpu_rlt;
    out->key_index   =  ((p_cpu_res->lu_idx_14_21<<14)|p_cpu_res->lu_idx_0_13);
    out->is_full     = p_cpu_res->pending;
    out->is_conflict = p_cpu_res->conflict;
#if (SDB_DISABLE != SDB_MODE)
    if(DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_FORCE_STORE_SDB))
    {
        uint8 enable = 0;
        uint8* p_sdb_data;

        drv_sdb_get_table_enable(lchip, acc_in->tbl_id, &enable);
        if(0 == enable)
        {
            return DRV_E_NONE;
        }
        if(out->key_index >= DRV_CONST(DRV_FIB_HOST0_CAM_NUM))
        {
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, acc_in->tbl_id, out->key_index - DRV_CONST(DRV_FIB_HOST0_CAM_NUM), 
                                                     acc_in->data, DYNAMIC_TABLE_UNIT_SIZE(lchip, acc_in->tbl_id), acc_in->oper_bmp);
        }
        else
        {
            p_sdb_data = (uint8*)drv_sdb_read(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
            sal_memcpy(p_sdb_data+((out->key_index&0x3)*TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2), acc_in->data, (TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2));
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, p_sdb_data, 
                                                     TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
        }
    }
#endif

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_result_del_mac_by_key(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    ds_fib_hash_cpu_res_tmm_t* p_cpu_res = NULL;
    
    p_cpu_res = (ds_fib_hash_cpu_res_tmm_t*)fib_acc_cpu_rlt;
    out->key_index   =  ((p_cpu_res->lu_idx_14_21<<14)|p_cpu_res->lu_idx_0_13);
    out->is_hit      = p_cpu_res->key_hit;
    out->is_conflict = p_cpu_res->conflict;
#if (SDB_DISABLE != SDB_MODE)
    if(DRV_IS_BIT_SET(acc_in->flag, DRV_ACC_FORCE_STORE_SDB))
    {
        uint8 enable = 0;
        uint8* p_sdb_data;

        drv_sdb_get_table_enable(lchip, acc_in->tbl_id, &enable);
        if(0 == enable)
        {
            return DRV_E_NONE;
        }
        if(out->key_index >= DRV_CONST(DRV_FIB_HOST0_CAM_NUM))
        {
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, acc_in->tbl_id, out->key_index - DRV_CONST(DRV_FIB_HOST0_CAM_NUM), 
                                     acc_in->data, DYNAMIC_TABLE_UNIT_SIZE(lchip, acc_in->tbl_id), acc_in->oper_bmp);
        }
        else
        {
            p_sdb_data = (uint8*)drv_sdb_read(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
            sal_memcpy(p_sdb_data+((out->key_index&0x3)*TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2), acc_in->data, (TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t)>>2));
            DRV_MCHIP_SDB_API(lchip)->drv_sdb_write_api(lchip, DsFibHost0HashMacCam_t, out->key_index>>2, p_sdb_data, 
                                     TABLE_ENTRY_SIZE(lchip, DsFibHost0HashMacCam_t), acc_in->oper_bmp);
        }
    }
#endif
    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_result_lkp_mac_by_key(uint8 lchip,drv_acc_in_t* acc_in, uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    ds_fib_hash_cpu_res_tmm_t* p_cpu_res = NULL;
    
    p_cpu_res = (ds_fib_hash_cpu_res_tmm_t*)fib_acc_cpu_rlt;
    out->key_index   =  ((p_cpu_res->lu_idx_14_21<<14)|p_cpu_res->lu_idx_0_13);
    out->is_pending  = p_cpu_res->pending;
    out->is_hit      = p_cpu_res->key_hit;
    out->is_conflict = p_cpu_res->conflict_valid;
    out->ad_index    = p_cpu_res->ds_idx;

    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_result_dump_mac(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    ds_fib_hash_cpu_res_tmm_t* p_cpu_res = NULL;
    uint32 confict = 0;
    uint32 pending = 0;

    p_cpu_res = (ds_fib_hash_cpu_res_tmm_t*)fib_acc_cpu_rlt;
    confict = p_cpu_res->conflict;
    pending = p_cpu_res->pending;

    out->key_index = ((p_cpu_res->lu_idx_14_21<<14)|p_cpu_res->lu_idx_0_13);
    out->is_full   = (confict && (!pending));

    if (DRV_IS_DUET2(lchip))
    {
        out->is_end = confict && pending;
    }
    else
    {
        out->is_end = (out->key_index == ((uint32)TABLE_MAX_INDEX(lchip,  DsFibHost0MacHashKey_t) + 32 - 1));
    }

    out->query_cnt      = p_cpu_res->ds_idx;
    return DRV_E_NONE;
}

STATIC int32
_drv_tmm_acc_result_flex(uint8 lchip, drv_acc_in_t* acc_in,uint32* fib_acc_cpu_rlt, drv_acc_out_t* out)
{
    ds_fib_hash_cpu_res_tmm_t* p_cpu_res = NULL;

    p_cpu_res = (ds_fib_hash_cpu_res_tmm_t*)fib_acc_cpu_rlt;
    out->key_index = (((p_cpu_res->lu_idx_14_21&0xff)<<14)|p_cpu_res->lu_idx_0_13);
    /**********
      conflict_f      pending_f
         0              0               exceed the max index of fdb table
         0              1               exceed user configured threshold
         1              0               only for dump fdb, means dma is full
         1              1               exceed the max index of fdb table
    *********/
    out->is_end = !(p_cpu_res->conflict ^ p_cpu_res->pending);
    out->query_cnt      = p_cpu_res->ds_idx;
    out->is_full = (p_cpu_res->conflict && !p_cpu_res->pending);
    return DRV_E_NONE;
}


static drv_mchip_ser_t drv_ser_api =
{
    drv_tmm_ser_get_mem_desc_index,
    drv_tmm_ser_dma_recover_tcam
};


int32
drv_tmm_ser_api_init(uint8 lchip)
{
    p_drv_master[lchip]->mchip_api.p_mchip_ser = &drv_ser_api;

    return DRV_E_NONE;
}

int32
drv_tmm_app_api_init(uint8 lchip)
{
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ADD][0] = _drv_tmm_acc_prepare_write_mac_by_idx;     
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_ADD][1] = _drv_tmm_acc_prepare_write_mac_by_key;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DEL][0] = _drv_tmm_acc_prepare_del_mac_by_idx;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DEL][1] = _drv_tmm_acc_prepare_del_mac_by_key;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_LOOKUP][0] = _drv_tmm_acc_prepare_lkp_fib0_by_idx;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_LOOKUP][1] = _drv_tmm_acc_prepare_lkp_mac_by_key;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP][0] = _drv_tmm_acc_prepare_dump;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_DUMP][1] = _drv_tmm_acc_prepare_dump;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH][0] = _drv_tmm_acc_prepare_flush;
    p_drv_master[lchip]->fdb_pre_cb[DRV_ACC_TYPE_FLUSH][1] = _drv_tmm_acc_prepare_flush;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_ADD][1] = _drv_tmm_acc_result_write_mac_by_key;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DEL][1] = _drv_tmm_acc_result_del_mac_by_key;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_LOOKUP][1] = _drv_tmm_acc_result_lkp_mac_by_key;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP][0] = _drv_tmm_acc_result_dump_mac;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP][1] = _drv_tmm_acc_result_dump_mac;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP_FLEX][0] = _drv_tmm_acc_result_flex;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_DUMP_FLEX][1] = _drv_tmm_acc_result_flex;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_FLEX][0] = _drv_tmm_acc_result_flex;
    p_drv_master[lchip]->fdb_rst_cb[DRV_ACC_TYPE_FLUSH_FLEX][1] = _drv_tmm_acc_result_flex;
    p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_USERID] = _drv_tmm_acc_prepare_userid_by_key;
    p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_EGRESS_SCL] =_drv_tmm_acc_prepare_egress_scl_by_key;
    p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FLOW] =_drv_tmm_acc_prepare_fib_hash_by_key;
    p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST1] =_drv_tmm_acc_prepare_fib_hash_by_key;
    p_drv_master[lchip]->acc_pre_cb[DRV_ACC_HASH_MODULE_FIB_HOST0] =_drv_tmm_acc_prepare_fib_hash_by_key;

    return DRV_E_NONE;
}


#endif


